1. The Field of the Invention
The present invention relates to the manufacture of semiconductor circuit devices. More particularly, the present invention is directed to methods for inhibiting outgrowth of titanium silicide between the gate electrode and the source/drain regions of standard MOS transistor structures by depositing a nitrogen-rich titanium nitride (TiN) layer on a titanium layer prior to silicidation.
2. Technology Review
Silicon semiconductor devices, such as standard MOS transistor structures, commonly include a silicide layer to provide a uniform electrical contact to gate, source, and drain electrodes. In the standard procedure for forming the silicide layers, titanium is deposited over a MOS transistor structure (typically having a polysilicon gate electrode, source/drain regions, and spacer oxides), followed by annealing in a nitrogen atmosphere. Silicon from the gate electrode and from the source/drain regions reacts with the titanium to form titanium silicide. Silicon dioxide is relatively unreactive with titanium when compared with silicon.
The furnace temperature and exposure time of the semiconductor device during the annealing process must be carefully controlled to prevent outgrowth of the titanium silicide from the gate electrode as well as suction of the silicon from the source/drain region to form short circuit paths between the gate electrode and the source/drain contacts.
The formation of short circuit paths between the gate electrode and the source/drain contacts represents a potential major obstacle for further shrinkage of semiconductor devices for ULSI applications. Therefore, it will be appreciated that what is needed in the art are methods for inhibiting outgrowth of titanium silicide between the gate electrode and the source/drain regions of integrated circuit devices, thereby inhibiting the formation of short circuit paths between the gate electrode and the source/drain contacts.
Such methods for inhibiting the outgrowth of silicide between the gate electrode and the source/drain regions of integrated circuit devices are disclosed and claimed herein.